The present application relates to spread spectrum at phase lock loop (PLL) feedback path methods and systems and more particularly to spread spectrum digital clock circuits having reduced electromagnetic interference (EMI) emissions.
Many digital circuits require clock signals for synchronization. Such digital circuits include microprocessors, which are operating at higher and higher frequencies, making them increasingly susceptible to EMI. One known solution adds weight, complexity, and cost by reducing EMI with filters, shielded boxes, or ferrite elements.
U.S. Pat. No. 5,488,627 discloses a spread spectrum (SS) clock generator which reduces the spectral amplitude of EMI components over a substantial bandwidth. According to this patent, a phase locked loop (PLL) is used to multiply the frequency of a selected low frequency crystal. The PLL is used to force the frequency of a voltage controlled oscillator (VCO) to change until a divided output signal and a divided reference signal match the phase detector input. However, the clock circuit has a noisy envelope.
Accordingly, it is desirable to develop a clock signal which operates at a reduced noise level and reduced EMI for applications including but not limited to computers, automotive devices and systems, fax/modems, copiers, scanners, printers, and set-top boxes, for example, without requiring costly shielding.
According to the present invention, a plurality of four bit modulation read only memory (ROM) codes are generated with a phase lock loop (PLL) feedback divider. The output of a single phase lock loop is modulated to spread the bandwidth of a synthesized clock signal according to the present invention. By spreading the bandwidth of the synthesized clock signal, the peak amplitude of the synthesized clock signal is decreased with respect to its fundamental frequency and its harmonics. As a result of reducing the peak amplitude of the synthesized clock signal, the radiated electromagnetic emission level is significantly lower than in the case of a typical narrow band signal produced by conventional frequency generators. Thus, spread spectrum clock generation according to the present invention is effective for lowering a signal""s amplitude by increasing its bandwidth. According to a method of the present invention, input phase lock loop system data is received as to selected phase lock loop characteristics. Next, a continuous feedback divider is used, and a bandwidth and system stability calculation is performed. Then, according to the present invention, a state variable system is determined and a numerical model for programming by finite differences is conducted. Next, an initial state setup is developed. Then, a next possible state calculation is performed. A best path is determined to produce output data and ROM code by a least squares error method.
A spread spectrum clock generator according to the present invention enables reduction of electromagnetic emission according to one embodiment by as much as 12 dB. An actual attenuation of emissions is a function of frequency according to the present invention. According to one embodiment of the present invention, emission attenuation is greatest at the higher frequencies of the attenuation range. With spread spectrum clock generation according to the present invention, board layout shielding can be reduced or eliminated for selected printed circuit boards. According to the present invention shielding requirements are reduced or eliminated, resulting in lower costs and lighter weight products.